High Speed ACSU Architecture for Viterbi Decoder Using T-Algorithm
نویسنده
چکیده
In this paper, we propose an efficient architecture based on pre-computation for Viterbi decoders incorporating Talgorithm. Through optimization at both algorithm level and architecture level, the new architecture greatly shortens the long critical path introduced by the conventional T-algorithm. The design example provided in this work demonstrates more than twice improvement in clock speed with negligible computation overhead while maintaining decoding performance.
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